Performance and Energy Impact of Instruction-Level Value Predictor Filtering

This work evaluates value predictor access filtering and its effects on performance and dynamic energy consumption in a wide-issue, high-frequency processor. New and previously proposed filtering strategies are analyzed with realistic predictor constraints, such as port restrictions and table access latency. Filters restrict access to the value predictor for instructions with unconsumed predictions, poorly predicted instructions, and quickly executing instructions. Read access filtering improves speedup due to value prediction from 16.1% to 23.6%, while reducing dynamic value predictor reads by 31.3%. Adding write filtering decreases update activity by 78.6%, while still providing 14.8% speedup. The overall reduction in activity leads to a value predictor energy consummption decrease